Plasma etching processes for advanced CMOS devices

Since its creation in 1999, LTM etch team has concentrated its efforts on the development and characterization of plasma etching processes to pattern complex stacks of materials involved in CMOS devices. At each technological node, the complexity of the CMOS architecture keeps increasing, several thin layers of new materials are introduced in the stacks, adding the stringent requirements imposed on the critical dimension control at the nanometer scale. All these changes increase the complexity of plasma etching processes and require a deeper understanding of the etch mechanisms involved in such complex stacks. Thanks to our strong cooperation with industry (STMicroelectronics CEA-LETI, and Applied Materials), the LTM etch team has made major breakthroughs in the field of plasma etching processes and their characterizations.

To carry out these studies, LTM etch team has at its disposal two powerful industrial etching platforms from Applied Materials located in the CEA-LETI clean room, the centura 5200 accepting 200 mm diameter wafers and the centura 300 accepting 300mm wafers. Both platforms have been equipped with industrial plasma etch chambers (inductive and capacitive coupled plasma sources), modified to accept in-situ diagnostics (XPS), mass spectrometry, ellipsometry, UV absorption, optical emission). LTM has also accessed to various ex-situ characterization tools thanks to its close collaboration with CEA-LETI (SEM, FTIR, 3D-AFM..).

Four main topics of research are conducted to face the challenges related to CMOS devices downscaling:

Plasma etching processes for advanced high-k/metal gate

Development and characterization of plasma processes dedicated to the etching of new materials (HfO2, TiN, W, TaC, Mo..) introduced in advanced high-k/metal gate stacks
Key issues addressed: Critical dimension control at the nanometer range, etch selectivity, and etch chemistry compatibility between Poly silicon, metals and high-k materials
Study of metal etching products deposition on the chamber walls and introduction of appropriate cleaning and conditioning reactor wall strategies

Linewidth roughness (LWR) transfer during plasma etching processes

This very hot topic is definitely limiting our ability to shrink nanoelectronics devices
Exploitation of the innovative CD-AFM technique available at the CEA-LETI to reconstruct pattern profile in 3D and monitor the LWR: LTM is the only academic laboratory worldwide to use this technique, giving access to unique experimental results.
Study of plasma treatments to improve 193nm photoresist LWR directly after lithography
Investigation of the LWR transfer during the patterning of complex stacks involved in front end and back end processes

Plasma processes for porous SiOCH integration in advanced interconnect levels

Development and characterization of plasma processes for porous SiOCH integration in advanced interconnect levels
Key issues : Low-k SiOCH modification during plasma etching, Critical dimension and profile control, pattern surface and sidewalls roughening, post etching residues
Introduction of scatterometric porosimetry to monitor ultra Low k modification during plasma etching processes and post etching treatment processes

Fundamental studies of plasmas and plasma-reactor wall interactions

Fundamental studies of the plasmas and plasma/chamber walls interactions
Introduction of innovative characterization techniques of the plasma and plasma/surface interactions to increase the team expertise in plasma etching processes
Introduction of the “Floating sample” technique to monitor etch product deposition on the chamber walls and optimize reactor cleaning and conditioning strategies
Use of LED as light source for UV absorption to monitor in real time the radical concentrations in the plasma as a function of subtle change of the chamber wall coatings